Recently, techniques for forming a semiconductor layer with a crystal structure (which will be referred to herein as a “crystalline semiconductor layer”) by crystallizing an amorphous semiconductor layer that has been deposited on an insulating substrate such as a glass substrate have been researched extensively. Examples of such crystalline semiconductor layers include polycrystalline semiconductor layers and microcrystalline semiconductor layers. A thin-film transistor (TFT) that has been fabricated with a crystalline semiconductor layer has far higher carrier mobility than a TFT that has been fabricated with an amorphous semiconductor layer. For that reason, pixel TFTs for the display area on an active-matrix substrate with a built-in driver, which can be used effectively in a display device (such as a liquid crystal display device), and driver TFTs for the peripheral area thereof are fabricated using a crystalline semiconductor layer.
As a technique for crystallizing an amorphous semiconductor layer, a continuous grain silicon (CGS) process, in which the amorphous semiconductor layer is heated with a catalyst element (such as nickel) added thereto, is known. According to such a technique, a crystalline semiconductor layer of good quality with aligned crystallographic plane orientations can be obtained in a short time and at a low temperature. However, in a situation where a crystalline semiconductor layer has been formed by the CGS process, if the catalyst element remains in the channel region, then the OFF-state current of TFTs might increase suddenly. To suppress such a sudden increase in OFF-state current, a countermeasure for providing a gettering region to remove the catalyst element by a gettering process is known (see Patent Document No. 1, for example). In the semiconductor device disclosed in Patent Document No. 1, a gettering region, to which a Group V element such as phosphorus has been introduced, is arranged around source/drain regions with contact portions. And a catalyst element remaining in the channel region of a crystalline semiconductor layer is removed under heat by the gettering process, thereby suppressing a sudden increase in the OFF-state current of a TFT.                Patent Document No. 1: Japanese Patent Application Laid-Open Publication No. 2006-128469        